РОЗРОБКА КОНВЕЄРНОГО ПРОЦЕСОРА. Лабораторна робота з Основи проектування цифрових засобів на ПЛІС. Робота № 527551

РОЗРОБКА КОНВЕЄРНОГО ПРОЦЕСОРА

Інформація про навчальний заклад

ВУЗ:

Національний університет Львівська політехніка

Інститут:

ІКТА

Факультет:

Комп'ютерна інженерія

Кафедра:

ЕОМ

Інформація про роботу

Рік:

2015

Тип роботи:

Лабораторна робота

Предмет:

Основи проектування цифрових засобів на ПЛІС

Група:

КІ 41

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МІНІСТЕРСТВО ОСВІТИ І НАУКИ УКРАЇНИ НАЦІОНАЛЬНИЙ УНІВЕРСИТЕТ “ЛЬВІВСЬКА ПОЛІТЕХНІКА” / Лабораторна робота №3 з дисципліни "Основи проектування цифрових засобів на ПЛІС" Тема: РОЗРОБКА КОНВЕЄРНОГО ПРОЦЕСОРА Мета роботи: розробити конвеєрний процесор. Функція КОП: 5*a*b + c*d / Рис. 1. Реалізована схема. Код конвеєрного процесора library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity gvv_pipeline_mult is Port ( gvv_clk : in STD_LOGIC; gvv_reset : in STD_LOGIC; gvv_a : in STD_LOGIC_VECTOR (7 downto 0); gvv_b : in STD_LOGIC_VECTOR (7 downto 0); gvv_d : in STD_LOGIC_VECTOR (7 downto 0); gvv_y : out STD_LOGIC_VECTOR (15 downto 0)); end gvv_pipeline_mult; architecture Behavioral of gvv_pipeline_mult is constant WIDTH: integer:=8; signal gvv_a1_reg, gvv_a2_reg, gvv_a3_reg, gvv_a4_reg, gvv_a5_reg, gvv_a6_reg : std_logic_vector(WIDTH-1 downto 0); signal gvv_a0, gvv_a1_next, gvv_a2_next, gvv_a3_next, gvv_a4_next, gvv_a5_next, gvv_a6_next : std_logic_vector(WIDTH-1 downto 0); signal gvv_b1_reg, gvv_b2_reg, gvv_b3_reg, gvv_b4_reg, gvv_b5_reg, gvv_b6_reg: std_logic_vector(WIDTH-1 downto 0); signal gvv_b0, gvv_b1_next, gvv_b2_next, gvv_b3_next, gvv_b4_next, gvv_b5_next, gvv_b6_next : std_logic_vector(WIDTH-1 downto 0); signal gvv_bv0, gvv_bv1, gvv_bv2, gvv_bv3, gvv_bv4, gvv_bv5, gvv_bv6, gvv_bv7 : std_logic_vector(WIDTH-1 downto 0); signal gvv_bp0, gvv_bp1, gvv_bp2, gvv_bp3, gvv_bp4, gvv_bp5, gvv_bp6, gvv_bp7 : unsigned(2*WIDTH - 1 downto 0); signal gvv_pp1_reg, gvv_pp2_reg, gvv_pp3_reg, gvv_pp4_reg, gvv_pp5_reg, gvv_pp6_reg, gvv_pp7_reg : unsigned(2*WIDTH - 1 downto 0); signal gvv_pp0, gvv_pp1_next, gvv_pp2_next, gvv_pp3_next, gvv_pp4_next, gvv_pp5_next, gvv_pp6_next, gvv_pp7_next: unsigned(2*WIDTH - 1 downto 0); signal gvv_d1_reg, gvv_d2_reg, gvv_d3_reg, gvv_d4_reg, gvv_d5_reg, gvv_d6_reg : std_logic_vector(WIDTH-1 downto 0); signal gvv_d0, gvv_d1_next, gvv_d2_next, gvv_d3_next, gvv_d4_next, gvv_d5_next, gvv_d6_next : std_logic_vector(WIDTH-1 downto 0); signal gvv_dpp1_reg, gvv_dpp2_reg, gvv_dpp3_reg, gvv_dpp4_reg, gvv_dpp5_reg, gvv_dpp6_reg, gvv_dpp7_reg : unsigned(2*WIDTH - 1 downto 0); signal gvv_dpp0, gvv_dpp1_next, gvv_dpp2_next, gvv_dpp3_next, gvv_dpp4_next, gvv_dpp5_next, gvv_dpp6_next, gvv_dpp7_next: unsigned(2*WIDTH - 1 downto 0); signal gvv_dv0, gvv_dv1, gvv_dv2, gvv_dv3, gvv_dv4, gvv_dv5, gvv_dv6, gvv_dv7 : std_logic_vector(WIDTH-1 downto 0); signal gvv_dp0, gvv_dp1, gvv_dp2, gvv_dp3, gvv_dp4, gvv_dp5, gvv_dp6, gvv_dp7 : unsigned(2*WIDTH - 1 downto 0); signal gvv_w : unsigned (15 downto 0); begin -- pipeline registers process(gvv_clk,gvv_reset) begin if (gvv_reset = '1') then gvv_pp1_reg <= (others => '0'); gvv_pp2_reg <= (others => '0'); gvv_pp3_reg <= (others => '0'); gvv_pp4_reg <= (others => '0'); gvv_pp5_reg <= (others => '0'); gvv_pp6_reg <= (others => '0'); gvv_pp7_reg <= (others => '0'); gvv_a1_reg <= (others => '0'); gvv_a2_reg <= (others => '0'); gvv_a3_reg <= (others => '0'); gvv_a4_reg <= (others => '0'); gvv_a5_reg <= (others => '0'); gvv_a6_reg <= (others => '0'); gvv_b1_reg <= (others => '0'); gvv_b2_reg <= (others => '0'); gvv_b3_reg <= (others => '0'); gvv_b4_reg <= (others => '0'); gvv_b5_reg <= (others => '0'); gvv_b6_reg <= (others => '0'); gvv_dpp1_reg <= (others => '0'); gvv_dpp2_reg <= (others => '0'); gvv_dpp3_reg <= (others => '0'); gvv_dpp4_reg <= (others => '0'); gvv_dpp5_reg <= (others => '0'); gvv_dpp6_reg <= (others => '0'); gvv_dpp7_reg <= (others => '0'); gvv_d1_reg <= (others => '0'); gvv_d2_reg <= (others => '0'); gvv_d3_reg <= (others => '0'); gvv_d4_reg <= (others => '0'); gvv_d5_reg <= (others => '0'); gvv_d6_reg <= (others => '0'); elsif (gvv_clk'event and gvv_clk = '1') then gvv_pp1_reg <= gvv_pp1_next; gvv_pp2_reg <= gvv_pp2_next; gvv_pp3_reg <= gvv_pp3_next; gvv_pp4_reg <= gvv_pp4_next; gvv_pp5_reg <= gvv_pp5_next; gvv_pp6_reg <= gvv_pp6_next; gvv_pp7_reg <= gvv_pp7_next; gvv_a1_reg <= gvv_a1_next; gvv_a2_reg <= gvv_a2_next; gvv_a3_reg <= gvv_a3_next; gvv_a4_reg <= gvv_a4_next; gvv_a5_reg <= gvv_a5_next; gvv_a6_reg <= gvv_a6_next; gvv_b1_reg <= gvv_b1_next; gvv_b2_reg <= gvv_b2_next; gvv_b3_reg <= gvv_b3_next; gvv_b4_reg <= gvv_b4_next; gvv_b5_reg <= gvv_b5_next; gvv_b6_reg <= gvv_b6_next; gvv_dpp1_reg <= gvv_dpp1_next; gvv_dpp2_reg <= gvv_dpp2_next; gvv_dpp3_reg <= gvv_dpp3_next; gvv_dpp4_reg <= gvv_dpp4_next; gvv_dpp5_reg <= gvv_dpp5_next; gvv_dpp6_reg <= gvv_dpp6_next; gvv_dpp7_reg <= gvv_dpp7_next; gvv_d1_reg <= gvv_d1_next; gvv_d2_reg <= gvv_d2_next; gvv_d3_reg <= gvv_d3_next; gvv_d4_reg <= gvv_d4_next; gvv_d5_reg <= gvv_d5_next; gvv_d6_reg <= gvv_d6_next; end if; end process; -- stage 0 & 1 for pipeline gvv_bv0 <= (others => gvv_b(0)); gvv_bp0 <= unsigned("00000000" & (gvv_bv0 and gvv_a)); gvv_pp0 <= gvv_bp0; gvv_a0 <= gvv_a; gvv_b0 <= gvv_b; gvv_bv1 <= (others => gvv_b0(1)); gvv_bp1 <= unsigned("0000000" & (gvv_bv1 and gvv_a0) & "0"); gvv_pp1_next <= gvv_pp0 + gvv_bp1; gvv_a1_next <= gvv_a0; gvv_b1_next <= gvv_b0; gvv_dv0 <= (others => gvv_d(0)); gvv_dp0 <= unsigned("00000000" & (gvv_dv0 and gvv_d)); gvv_dpp0 <= gvv_dp0; gvv_d0 <= gvv_d; gvv_dv1 <= (others => gvv_d0(1)); gvv_dp1 <= unsigned("0000000" & (gvv_dv1 and gvv_d0) & "0"); gvv_dpp1_next <= gvv_dpp0 + gvv_dp1; gvv_d1_next <= gvv_d0; -- stage 2 gvv_bv2 <= (others => gvv_b1_reg(2)); gvv_bp2 <= unsigned("000000" & (gvv_bv2 and gvv_a1_reg) & "00"); gvv_pp2_next <= gvv_pp1_reg + gvv_bp2; gvv_a2_next <= gvv_a1_reg; gvv_b2_next <= gvv_b1_reg; gvv_dv2 <= (others => gvv_d1_reg(2)); gvv_dp2 <= unsigned("000000" & (gvv_dv2 and gvv_d1_reg) & "00"); gvv_dpp2_next <= gvv_dpp1_reg + gvv_dp2; gvv_d2_next <= gvv_d1_reg; -- stage 3 gvv_bv3 <= (others => gvv_b2_reg(3)); gvv_bp3 <= unsigned("00000" & (gvv_bv3 and gvv_a2_reg) & "000"); gvv_pp3_next <= gvv_pp2_reg + gvv_bp3; gvv_a3_next <= gvv_a2_reg; gvv_b3_next <= gvv_b2_reg; gvv_dv3 <= (others => gvv_d2_reg(3)); gvv_dp3 <= unsigned("00000" & (gvv_dv3 and gvv_d2_reg) & "000"); gvv_dpp3_next <= gvv_dpp2_reg + gvv_dp3; gvv_d3_next <= gvv_d2_reg; -- stage 4 gvv_bv4 <= (others => gvv_b3_reg(4)); gvv_bp4 <= unsigned("0000" & (gvv_bv4 and gvv_a3_reg) & "0000"); gvv_pp4_next <= gvv_pp3_reg + gvv_bp4; gvv_a4_next <= gvv_a3_reg; gvv_b4_next <= gvv_b3_reg; gvv_dv4 <= (others => gvv_d3_reg(4)); gvv_dp4 <= unsigned("0000" & (gvv_dv4 and gvv_d3_reg) & "0000"); gvv_dpp4_next <= gvv_dpp3_reg + gvv_dp4; gvv_d4_next <= gvv_d3_reg; -- stage 5 gvv_bv5 <= (others => gvv_b4_reg(5)); gvv_bp5 <= unsigned("000" & (gvv_bv5 and gvv_a4_reg) & "00000"); gvv_pp5_next <= gvv_pp4_reg + gvv_bp5; gvv_a5_next <= gvv_a4_reg; gvv_b5_next <= gvv_b4_reg; gvv_dv5 <= (others => gvv_d4_reg(5)); gvv_dp5 <= unsigned("000" & (gvv_dv5 and gvv_d4_reg) & "00000"); gvv_dpp5_next <= gvv_dpp4_reg + gvv_dp5; gvv_d5_next <= gvv_d4_reg; -- stage 6 gvv_bv6 <= (others => gvv_b5_reg(6)); gvv_bp6 <= unsigned("00" & (gvv_bv6 and gvv_a5_reg) & "000000"); gvv_pp6_next <= gvv_pp5_reg + gvv_bp6; gvv_a6_next <= gvv_a5_reg; gvv_b6_next <= gvv_b5_reg; gvv_dv6 <= (others => gvv_d5_reg(6)); gvv_dp6 <= unsigned("00" & (gvv_dv6 and gvv_d5_reg) & "000000"); gvv_dpp6_next <= gvv_dpp5_reg + gvv_dp6; gvv_d6_next <= gvv_d5_reg; -- stage 7 gvv_bv7 <= (others => gvv_b6_reg(7)); gvv_bp7 <= unsigned("0" & (gvv_bv7 and gvv_a6_reg) & "0000000"); gvv_pp7_next <= gvv_pp6_reg + gvv_bp7; gvv_dv7 <= (others => gvv_d6_reg(7)); gvv_dp7 <= unsigned("0" & (gvv_dv7 and gvv_d6_reg) & "0000000"); gvv_dpp7_next <= gvv_dpp6_reg + gvv_dp7; gvv_w <= gvv_pp7_next+gvv_dpp7_next; -- result gvv_y <= std_logic_vector(gvv_w); end Behavioral; END; / Рис. 3. Часова діаграма Звіт для Module1 ========================================================================= * HDL Synthesis * ========================================================================= Performing bidirectional port resolution... Synthesizing Unit <gvv_pipeline_mult>. Related source file is "C:/Xilinx/hjk/coneeer.vhd". WARNING:Xst:646 - Signal <gvv_pp7_reg> is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal <gvv_dpp7_reg> is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal <gvv_b6_reg<6:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Found 8-bit register for signal <gvv_a1_reg>. Found 8-bit register for signal <gvv_a2_reg>. Found 8-bit register for signal <gvv_a3_reg>. Found 8-bit register for signal <gvv_a4_reg>. Found 8-bit register for signal <gvv_a5_reg>. Found 8-bit register for signal <gvv_a6_reg>. Found 8-bit register for signal <gvv_b1_reg>. Found 8-bit register for signal <gvv_b2_reg>. Found 8-bit register for signal <gvv_b3_reg>. Found 8-bit register for signal <gvv_b4_reg>. Found 8-bit register for signal <gvv_b5_reg>. Found 8-bit register for signal <gvv_b6_reg>. Found 8-bit register for signal <gvv_d1_reg>. Found 8-bit register for signal <gvv_d2_reg>. Found 8-bit register for signal <gvv_d3_reg>. Found 8-bit register for signal <gvv_d4_reg>. Found 8-bit register for signal <gvv_d5_reg>. Found 8-bit register for signal <gvv_d6_reg>. Found 16-bit adder for signal <gvv_dpp1_next>. Found 16-bit register for signal <gvv_dpp1_reg>. Found 16-bit adder for signal <gvv_dpp2_next>. Found 16-bit register for signal <gvv_dpp2_reg>. Found 16-bit adder for signal <gvv_dpp3_next>. Found 16-bit register for signal <gvv_dpp3_reg>. Found 16-bit adder for signal <gvv_dpp4_next>. Found 16-bit register for signal <gvv_dpp4_reg>. Found 16-bit adder for signal <gvv_dpp5_next>. Found 16-bit register for signal <gvv_dpp5_reg>. Found 16-bit adder for signal <gvv_dpp6_next>. Found 16-bit register for signal <gvv_dpp6_reg>. Found 16-bit adder for signal <gvv_dpp7_next>. Found 16-bit adder for signal <gvv_pp1_next>. Found 16-bit register for signal <gvv_pp1_reg>. Found 16-bit adder for signal <gvv_pp2_next>. Found 16-bit register for signal <gvv_pp2_reg>. Found 16-bit adder for signal <gvv_pp3_next>. Found 16-bit register for signal <gvv_pp3_reg>. Found 16-bit adder for signal <gvv_pp4_next>. Found 16-bit register for signal <gvv_pp4_reg>. Found 16-bit adder for signal <gvv_pp5_next>. Found 16-bit register for signal <gvv_pp5_reg>. Found 16-bit adder for signal <gvv_pp6_next>. Found 16-bit register for signal <gvv_pp6_reg>. Found 16-bit adder for signal <gvv_pp7_next>. Found 16-bit adder for signal <gvv_w>. Summary: inferred 336 D-type flip-flop(s). inferred 15 Adder/Subtractor(s). Unit <gvv_pipeline_mult> synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Adders/Subtractors : 15 16-bit adder : 15 # Registers : 30 16-bit register : 12 8-bit register : 18 ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : gvv_pipeline_mult.ngr Top Level Output File Name : gvv_pipeline_mult Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs : 42 Cell Usage : # BELS : 473 # BUF : 2 # GND : 1 # LUT1 : 2 # LUT2 : 185 # LUT3 : 2 # LUT4 : 34 # MULT_AND : 19 # MUXCY : 119 # MUXF5 : 1 # VCC : 1 # XORCY : 107 # FlipFlops/Latches : 250 # FD : 5 # FDC : 245 # Shift Registers : 5 # SRL16 : 5 # Clock Buffers : 1 # BUFGP : 1 # IO Buffers : 41 # IBUF : 25 # OBUF : 16 ========================================================================= Device utilization summary: --------------------------- Selected Device : 2s50pq208-5 Number of Slices: 162 out of 768 21% Number of Slice Flip Flops: 250 out of 1536 16% Number of 4 input LUTs: 228 out of 1536 14% Number used as logic: 223 Number used as Shift registers: 5 Number of IOs: 42 Number of bonded IOBs: 42 out of 140 30% Number of GCLKs: 1 out of 4 25% Висновок На цій лабораторній роботі я розробив конвеєрний процесор згідно завдання.

Лабораторна робота Основи проектування цифрових засобів на ПЛІС

30.12.2015 03:25

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